1. Field of Invention
The present invention relates to a thin film transistor, and more particularly to a process of manufacturing a thin film transistor.
2. Related Art
A liquid crystal display is constructed from a pair of substrates assembled opposite to each other to form a gap there between. A liquid crystal layer is sandwiched between the substrates. Each substrate has one electrode facing another electrode of the opposite substrate. When a voltage is applied on the two electrodes, an electric field is generated between the two electrodes. By changing the intensity and direction of this electric field, the orientation of the liquid crystal molecules in the liquid crystal layer is modified. The transmission of light through the liquid crystal layer thereby is controlled via the variation of the orientation of the liquid crystal molecules. Display patterns are thereby obtained on the liquid crystal display device.
FIG. 1 is a partially exploded view of a conventional liquid crystal display. The conventional liquid crystal display includes an upper substrate 5 and a lower substrate, 22 facing each other. A liquid crystal layer 15 is sandwiched between the substrates 5, 22. The upper substrate 5 includes a black matrix line 6, a color filter 7, and a common electrode 9. The black matrix line 6 forms a plurality of openings distributed in array. Each of the openings has a size fitting the color filter 7. The color filter 7 may be a red, green or blue color filter. The common electrode 9 is transparent and placed on the color filter 7. A gate line 12 and a data line 34 are formed on the lower substrate 22. The gate line 12 intersects with the data line to define a pixel region P. A thin film transistor T is an inverting element consisting of a gate electrode, a source electrode and a drain electrode. A plurality of thin film transistors T is respectively arranged in array in areas defined by the gate line 12 and the data line 34 (i.e., regions P). A pixel electrode 56 and a thin film transistor T in one P region connect to each other. The pixel electrode 56 is made of a transparent conductive material with good light transmission, such as indium-tin-oxide (ITO). Each pixel electrode 56 aligns with a corresponding color filter. The lower substrate 22 includes a plurality of thin film transistors T and a plurality of pixel electrodes 56 in array, to form an array substrate of the liquid crystal display.
When a scanning pulse scans the gate electrode of the thin film transistor via the gate line 12, a data signal is generated and sent to the source electrode of the thin film transistor via the data line 34.
The liquid crystal display is driven via the optical properties of the liquid crystal material. The liquid crystal material is a dielectric anisotropic material having controllable polarization properties. When an adequate voltage is applied on the liquid crystal layer, the liquid crystal molecules orientate to form a dipole in accordance with the direction of the electric field. The orientation of the liquid crystal molecules determines the transmission of light there through. Images on the liquid crystal display are typically generated by controlling the light transmission of the liquid crystal layer.
FIG. 2A to FIG. 2F are cross-sectional views illustrating a conventional process of producing a thin film transistor using five photo masks.
Referring to FIG. 2A, a first metal layer is formed on a substrate 100 by physical vapor deposition. The metal layer is made of aluminum, chromium or molybdenum. The substrate 100 is made of an insulating non-alkaline glass. Then, a first photo resist (not shown) is formed on the first metal layer. After first exposure and development processes are performed, using a first photo mask, dry or wet etching is performed to remove portions of the first metal layer and form a gate line 101 on the substrate 100. The first photo resist (not shown) on the gate line 101 then is removed.
Referring to FIG. 2B, a gate electrode insulator 102, a semiconductor layer 103, an ohmic contact layer 104 and a second photo resist (not shown) are subsequently formed on the gate line 101 by plasma enhanced chemical vapor deposition. After second exposure and development processes are performed using a second photo mask, a dry etching process is performed to remove portions of the semiconductor layer 103 and the ohmic contact layer 104 and form a predetermined island-shaped transistor region. Then, the second photo resist (not shown) is removed. The ohmic contact layer 104 is, for example, an N type heavily doped silicon layer. The gate electrode insulator 102 is, for example, a silicon nitride or silicon dioxide.
Referring to FIG. 2C, a second metal layer 105 is formed on the island-shaped transistor region of the substrate by physical vapor deposition. A third photo resist (not shown) is formed on the second metal layer 105. After the third exposure and development processes are performed using a third photo mask, dry or wet etching is performed to form a source electrode 105a and a drain electrode 105b on the island-shaped transistor region. The source electrode and the drain electrode are spaced apart from each other by a gap through which the ohmic contact layer 104 is exposed. The second metal layer 105 is made of aluminum, chromium or molybdenum.
Referring to FIG. 2D, using the third photo resist (not shown) on the source electrode 105a and the drain electrode 105b as a mask, a dry etching process is performed to remove a portion of the ohmic contact layer not covered by the third photo resist (not shown) on the source electrode 105a and the drain electrode 105b. It thereby exposes the semiconductor layer 103 so as to form a semiconductor channel 106 between the source electrode 105a and the drain electrode 105b. This process is called a back channel etching (BCE) process. Then the third photo resist (not shown) is removed.
Referring to FIG. 2E, a protection layer 107 is formed on the island-shaped transistor region of the substrate 100 by plasma enhanced chemical vapor deposition. Then a fourth photo resist (not shown) is formed on the protection layer 107. After the fourth exposure and development processes are performed, using a fourth photo mask, a dry etching process is performed to define a contact hole 108 in the protection layer 107 over the drain electrode 105b. Finally, the fourth photo resist (not shown) is removed. The protection layer 107 is made of, for example, silicon nitride or silicon dioxide.
Referring to FIG. 2F, a pixel electrode 109 is formed on the protection layer 107 by physical vapor deposition. A fifth photo resist (not shown) is formed on the pixel electrode 109. After the fifth exposure and development processes are performed, using a fifth photo mask, a wet etching process is performed to pattern the pixel electrode 109 so that the contact hole 108 connects to the drain electrode 105b. Finally, the fifth photo resist (not shown) is removed. The pixel electrode 109 is made of, for example, ITO.
FIG. 3 is a top view of a conventional thin film transistor. The process of the prior art has some disadvantages. When the semiconductor layer 103 is etched, the photo resist on the semiconductor shrinks under etching of the plasma, which exposes the semiconductor 103a near the island-shaped transistor region. The exposed portion of the semiconductor layer 103a may be oxidized into silicon dioxide that prevents the ohmic contact layer from being etched off. Therefore, a portion of the ohmic contact layer remains close to the channel, resulting in current leakage when the thin film transistor is turned off. Current leakage causes defects such as cross talk, flicker and spots.